The present invention relates in general to substrate manufacturing technologies and in particular to methods and apparatus for the optimization of ion energy control in a plasma processing system.
In the processing of a substrate, e.g., a semiconductor wafer or a glass panel such as one used in flat panel display manufacturing, plasma is often employed. As part of the processing of a substrate (chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor deposition, etc.) for example, the substrate is divided into a plurality of dies, or rectangular areas, each of which will become an integrated circuit. The substrate is then processed in a series of steps in which materials are selectively removed (etching) and deposited (deposition) in order to form electrical components thereon.
Integrated circuits are sequentially created by forming conductive patterns on dielectric layers on a substrate. In an exemplary plasma process, a substrate is coated with a thin film of hardened emulsion (i.e., such as a photoresist mask) prior to etching. Areas of the hardened emulsion are then selectively removed, causing parts of the underlying layer to become exposed. The substrate is then placed in a plasma processing chamber on a substrate support structure comprising a mono-polar or bi-polar electrode, called a chuck. Appropriate etchant source gases (e.g., C4F8, C4F6, CHF3, CH2F3, CF4, CH3F, C2F4, N2, O2, Ar, Xe, He, H2, Nh3, SF6, BCl3, Cl2, etc.) are then flowed into the chamber and struck by a set of RF frequencies to form a plasma to etch exposed areas of the substrate. By controlling the amount of ion energy in the plasma through adjustments in a set of RF frequencies, the etch process is optimized.
In a common substrate manufacturing method, known as dual damascene, dielectric layers are electrically connected by a conductive plug filling a via hole. Generally, an opening is formed in a dielectric layer, which is then filled with a conductive material (e.g., aluminum (Al), copper (Cu), etc.) that allows electrical contact between two sets of conductive patterns. This establishes electrical contact between two active regions on the substrate, such as a source/drain region. Excess conductive material on the surface of the dielectric layer is typically removed by chemical mechanical polishing (CMP).
There are generally two approaches manufacture dual damascene substrates: Via-First and Trench-First. In one example of the Via-First methodology, the substrate is first coated with photoresist and then the vias are lithographically patterned. Next, an anisotropic etch cuts through the surface cap material and etches down through the low K layer of the substrate, and stops on a silicon nitride barrier, just above the underlying metal layer. Next, the via photoresist layer is stripped, and the trench photoresist is applied and lithographically patterned. Some of the photoresist will remain in the bottom of the via and prevent the lower portion via from being over-etched during the trench etch process. A second anisotropic etch then cuts through the surface cap material and etches the low K material down to a desired depth. This etch forms the trench. The photoresist is then stripped and the Silicon Nitride barrier at the bottom of the via is opened with a very soft, low-energy etch that will not cause the underlying copper to sputter into the via. As described above, the trench and via are filled with a conductive material (e.g., aluminum (Al), Copper (Cu), etc.) and polished by chemical mechanical polishing (CMP). And although the via-first approach has been widely adopted for small geometry devices because it avoids the photoresist pooling effect that occurs when the trenches are formed before the vias, it is also prone to photoresist poisoning.
An alternate methodology is trench-first. In one example, the substrate is coated with photoresist and a trench lithographic pattern is applied. An anisotropic dry etch then cuts through the surface hard mask (again typically SiN, TiN or TaN) followed by stripping the photoresist. Another photoresist is applied over the trench hard mask and then the vias are lithographically patterned. A second anisotropic etch then cuts through cap layer and partially etches down into the low K material. This etch forms the partial vias. The photoresist is then stripped for trench etch over the vias with the hard mask. The trench etch then cuts through the cap layer and partially etches the low K material down to desired depth. This etch also clears via holes at the same time stopping on the final barrier located at the bottom of the via. The bottom barrier is then opened with a special etch. And unlike the via-first methodology, photoresist poisoning may be substantially less.
However, escalating requirements for high circuit density on substrates may be difficult to satisfy using current plasma processing technologies where sub-micron via contacts and trenches have high aspect ratios. The utilization of new low-k films and complex film stacks present a new set of challenges for dielectric etch processes and equipment.
To facilitate discussion, FIG. 1A illustrates an idealized cross-sectional view of a layer stack 100, representing the layers of an exemplar semiconductor IC, prior to a lithographic step. In the discussions that follow, terms such as “above” and “below,” which may be employed herein to discuss the spatial relationship among the layers, may, but need not always, denote a direct contact between the layers involved. It should be noted that other additional layers above, below, or between the layers shown may be present. Further, not all of the shown layers need necessarily be present and some or all may be substituted by other different layers.
At the bottom of layer stack 100, there is shown a layer 108, comprising SiO2. Above layer 108 is disposed a barrier layer 104, typically comprising nitride or carbide (SiN or SiC). Dual damascene substrates further comprise a set of metal layers including M1 109a-b, typically comprising aluminum or copper. Above the barrier layer 104, is disposed a intermediate dielectric (IMD) layer 106, comprising a low K material (e.g., SiOC, etc.). Above the IMD layer 106, there may be placed a cap layer 103, typically comprising SiO2. Above cap layer 103, there may be disposed a trench mask layer 102, typically comprising TiN, SiN, or TaN.
FIG. 1B shows a somewhat idealized cross-sectional view of layer stack 100 of FIG. 1A, after photoresist layer 110 and a BARC layer 112 is further added. FIG. 1C shows a somewhat idealized cross-sectional view of layer stack 100 of FIG. 1B after photoresist layer 110 and BARC layer 112 have been processed through lithography. In this example, a photoresist mask pattern is created with a set of trenches 114a-b. 
FIG. 1D shows the cross-sectional view of layer stack 100 of FIG. 1C after trench mask layer 101 has been processed in the plasma system, further extending trench 114a-b to cap layer 103. FIG. 1E shows the cross-sectional view of layer stack 100 of FIG. 1D, after photoresist layer 110 and a BARC layer 112 are removed.
FIG. 1F shows the cross-sectional view of layer stack 100 of FIG. 1E after a second photoresist layer 116 and a BARC layer 118 are disposed, in order to create a second metal layer and a via connecting it to the first metal layer 109a-b. FIG. 1G shows the cross-sectional view of layer stack 100 of FIG. 1F after the photoresist layer has been opened and an etch has been performed to partially etch into IMD layer 106 to create a via. FIG. 1H shows the cross-sectional view of layer stack 100 of FIG. 1G after photoresist layer 110 and BARC layer 112 have been stripped, and an additional etch process has been performed to extend the trench to a desired depth and etch through a via stopping on barrier layer 104. In FIG. 1I, the barrier layer 104 is etched through using, for example CH2F2, CH3F, etc. In FIG. 1J, a chemical mechanical polish process has been performed to polish layer stack 100 down to cap layer 103, and a conductive material (e.g., aluminum (Al), Copper (Cu), etc.) has been deposited to contact the existing M1 metal material.
In a typical plasma processing system, a first RF energy source may be employed to create a cloud of ions for the processing a substrate. Generally speaking, this first RF energy source may be said to be generating a source RF signal for dissociating the ions. In addition, there is another RF energy source for creating a bias with the plasma, and directing the plasma away from structures within the plasma processing system and toward the substrate. Generally speaking, this second RF energy source may be said to be generating a bias RF signal for controlling the ion energy.
For example, a dual frequency triode configuration may have a source RF generator at the top of the chamber, and a bias RF generator coupled to provide the bias RF signal to the substrate. Referring now to FIG. 2A, a simplified diagram of a dual frequency triode plasma processing system 200 is shown. A typical arrangement is to employ a substantially high frequency source RF generator 202 (e.g., 27 MHz, 60 MHz, or 100 MHz) to provide a corresponding source RF signal an upper electrode, and a substantially lower frequency bias RF generator 204 (e.g., 8 KHz, 2 MHz, or 3 MHz) to provide a corresponding bias RF signal to the lower electrode, which is coupled to a substrate.
A dual frequency diode configuration may have both the source and bias RF generators coupled to provide both source and bias RF signals to the substrate. Referring now to FIG. 2B, a simplified diagram of a dual frequency diode plasma processing system 250 is shown. A plasma 206 forms above the substrate, and is accelerated down into the substrate to physically bombard and etch silicon or other materials from the substrate by an electric field formed between the plasma and the negatively charged wafer. A typical arrangement is to provide both a substantially high frequency source RF generator 252 (e.g., 27 MHz, 60 MHz, or 100 MHz) and a substantially lower frequency bias RF generator 254 (e.g., 8 KHz, 2 MHz, or 3 MHz) to provide both the source RF signal and the bias RF signal to the lower electrode, which is coupled to a substrate.
Single frequency diode configuration may have a single bias RF sources coupled to provide the bias RF signal to the substrate. Referring now to FIG. 2C, a simplified diagram of a single frequency diode plasma processing system 270 is shown. A plasma 206 forms above the substrate, and is accelerated down into the substrate to physically bombard and etch silicon or other materials from the substrate by an electric field formed between the plasma and the negatively charged wafer. A typical arrangement is to provide a single frequency bias RF generator 252 (e.g., 13.56 MHz,) to provide a bias RF signal to the lower electrode, which is coupled to a substrate.
While not wishing to be bound by theory, fast moving electrons in the plasma generally tend to be absorbed by walls or other boundaries. In order to maintain a charge balance in the plasma, a thin positive ion sheath may be formed near each wall or boundary such as those proximate the substrate. This creates an electric field which tends to accelerate ions in the plasma into the wall or boundary with a substantial amount of energy. If the plasma is not properly optimized, faceting or corner sputtering (or erosion) occurs on the substrate surface. A facet is the result of a non-linear profile in the substrate, such as in a trench sidewall. A corner sputtering is a result of an undesirable removal of additional material, particularly of the material at the upper corners of the feature to be etched.
Accurate control of faceting and unwanted corner sputtering becomes critical in dual damascene etches, particularly in copper dual damascene etches in which no plugs or multiple hard masks are employed (e.g., in a trench-first dual damascene dielectric etch). Up to now, no attempts have been made to employ RF configuration, particularly RF configuration of the bias RF generator, to minimize faceting and unwanted corner sputtering, maximizing the process window, and obtaining the desired vertical etch profile.